1。Kintex UltraScale+產(chǎn)品優(yōu)勢(shì)，如：XCKU9P-L1FFVE900i
k xilinx kintex<ultrascale+}現(xiàn)場(chǎng)可編程陣列（fpa）具有多種電源選擇，可以在要求的系統(tǒng)性能和非常低的功耗之間達(dá)到最佳平衡。fpga是一種基于可配置邏輯塊（clb）矩陣的半導(dǎo)體器件，通過可編程互連系統(tǒng)連接。Kintex UltraScale+設(shè)備是數(shù)據(jù)包處理和DSP密集型功能的理想選擇，適用于從無線mimo技術(shù)到NX100G網(wǎng)絡(luò)和數(shù)據(jù)中心的各種應(yīng)用。
特性
可編程系統(tǒng)集成
高達(dá)1.2m的系統(tǒng)邏輯單元
用于片上存儲(chǔ)器集成的UltraRAM集成100G以太網(wǎng)MAC以支持RS-FEC和150G因特拉肯內(nèi)核
提高系統(tǒng)性能
o.3 teramac dsp計(jì)算性能
與kintex-7fpga相比，系統(tǒng)級(jí)性能功率比提高了兩倍以上。
o 16G和28G背板-支持各種收發(fā)器
o中速級(jí)支持2666MB/s DDR4
降低物料清單成本
o 12.5gb/s最低速度等極收發(fā)器
集成vcxo和fpll可以降低時(shí)鐘組件的成本。
降低總功耗
o.與7系列FPGAs相比，功耗降低了60%
o.電壓縮放選項(xiàng)支持高性能和低功耗
o.使用緊湊的邏輯單元封裝以降低動(dòng)態(tài)功耗
提高設(shè)計(jì)生產(chǎn)力
o使用vivado設(shè)計(jì)套件進(jìn)行協(xié)作優(yōu)化，以加速設(shè)計(jì)收斂
智能連接技術(shù)在智能ip集成中的應(yīng)用
112mhz點(diǎn)對(duì)點(diǎn)mwr調(diào)制解調(diào)器及數(shù)據(jù)包處理
_ 1GHz寬帶調(diào)制解調(diào)器和數(shù)據(jù)包處理
1. Kintex UltraScale + product advantages such as: XCKU9P-L1FFVE900I
K Xilinx Kintex < UltraScale+} Field Programmable Array (FPA) has a variety of power options, which can achieve the best balance between the required system performance and very low power consumption. The FPGA is a semiconductor device based on a configurable logic block (CLB) matrix connected through a programmable interconnection system. Kintex UltraScale + devices are ideal for data packet processing and DSP-intensive functions, and are suitable for applications ranging from wireless MIMO technology to Nx100G network and data center.
Characteristic
Programmable System Integration
Up to 1.2M System Logic Unit
UltraRAM for on-chip memory integrationO Integrating 100G Ethernet MAC to support RS-FEC and 150G Interlaken Kernel
Improving system performance
O.3 TeraMAC DSP Computing Performance
O. Compared with Kintex-7 FPGA, the system-level performance-power ratio has been improved by more than two times.
O 16G and 28G backboards - support various transceivers
O Medium Speed Class Supports 2666Mb/s DDR4
Reducing BOM costs
O 12.5Gb/s transceiver with the lowest speed equal pole
O. The integration of VCXO and fPLL can reduce the cost of clock components
Reduced total power consumption
O. Power consumption is reduced by 60% compared with 7 series of FPGAs
O. Voltage scaling options support high performance and low power consumption
O. Using compact logic unit encapsulation to reduce dynamic power consumption
Increased design productivity
O Collaborative optimization with Vivado Design Suite to accelerate design convergence
Application of Smart Connect Technology for Intelligent IP Integration
112 MHz Point-to-Point MWR Modem and Data Packet Processing
_1GHz eBand Modem and Data Packet Processing
