1 × 160 MHz Power Architecture® e200z4 Dual issue, 32-bit CPU
– Single precision floating point operations
– 8 KB instruction cache and 4 KB data cache
– Variable length encoding (VLE) for significant code
density improvements
• 1 x 80 MHz Power Architecture® e200z2 Single issue,
32-bit CPU
– Using variable length encoding (VLE) for
significant code size footprint reduction
• End to end ECC
– All bus masters, for example, cores, generate a
single error correction, double error detection
(SECDED) code for every bus transaction
– SECDED covers 64-bit data and 29-bit address
• Memory interfaces
– 3 MB on-chip flash memory supported with the
flash memory controller
– 3 x flash memory page buffers (3-port flash memory
controller)
– 384 KB on-chip SRAM across three RAM ports
• Audio
– Synchronous Audio Interface (SAI)
– Fractional clock dividers (FCD) operating in
conjunction with the SAI
• Configurable I/O domains supporting FlexCAN,
LINFlexD, Ethernet, and general I/O
• Supports wake-up from low power modes via the
WKPU controller
• On-chip voltage regulator (VREG)
• Debug functionality
– e200z2 core:NDI per IEEE-ISTO 5001-2008
Class3+
– e200z4 core: NDI per IEEE-ISTO 5001-2008 Class
3+
Timer
– 16 Periodic Interrupt Timers (PITs)
– Two System Timer Modules (STM)
– Three Software Watchdog Timers (SWT)
– 64 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels
• Device/board boundary Scan testing supported with Joint Test Action Group (JTAG) of IEEE 1149.1 and IEEE 1149.7
(CJTAG)
• Security
– Hardware Security Module (HSMv2)
– Password and Device Security (PASS) supporting advanced censorship and life-cycle management
– One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts
• Functional Safety
– ISO26262 ASIL-B compliance
• Multiple operating modes
– Includes enhanced low power operation
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