kintex-7 fpga 系列特性表:

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ACST67S

ACST67S

AIC1084-18PMTR

AM40N04-20D

AMC76381-2.5PKT

AMS1117-ADJ

AOD4185L

B0530W

B0540W

B200NF04L

kintex-7 fpga主要特性:

twice the price-performance, lower cost

• many performance-boosting innovations including industry-leading 1,866mbps memory interface; 639mhz dsp48e1 slices with high performance filtering capabilities; six-input look-up table

• 1833mbps memory interfaces

• lvds connectivity at 1.6g

• up to 1,920 dsp slices

• package optimized to line rate performance

memory controller innovations

• dedicated hard ip implementation of the memory phy, for simplified interfacing to external ddr memory

• a flexible, soft controller enabled by high-performance logic for calibration, access methods, and system interfaces

• high-speed pci express hard and soft ip

• integrated hard ip for pci express, with full support for pci express endpoint and root port configurations

• hard ip support for up to eight pci express gen1 and gen2 channels

• soft ip support for up to eight pci express gen3 channels

maximize connectivity and stay within budget

• kintex-7 fpgas let designers choose a package with the right combination of price and performance for the application

• family price points each maximize throughput (6.6gbps and 12.5gbps transceivers)

• maximize performance with regular flip-chip bga packaging offering highest signal integrity and up to 32 high-speed gtx transceivers (12.5gbps line rates)

• minimize costs with bare-die flip-chip bga packaging that delivers high signal integrity and robust thermal characteristics (up to 6.6gbps line rates)half the power consumption

• hpl process cuts power in half compared to alternative 28nm high-performance (hp) process

• low 1.0v core voltage (optional 0.9v core voltage option for some devices) translates into lower system power, lower cooling required, and more “green” designs

•additional power reductions from intelligent clock gating and fifth generation partial reconfiguration

kintex-7 fpgas offer the best price-performance so designers can meet stringent latency requirements for lte baseband processing in a common platform.

• programmability enables a cost-effective common platform supporting multiple air interfaces such as lte, wimax, and wcdma

• reduce total cost of ownership with the ability to scale and reuse designs from picocell to macrocell

• 3x capacity at the same cost of previous-generation fpgas while consuming 40% less power

• support for 9.8gbps cpri/obsai for high throughput

• support for 6.144gbps cpri/obsai in a low-cost package option

圖1.單片lte基帶(2x4mimo)框圖

support for 6.144gbps cpri/obsai in a low-cost package optionhigh i/o bandwidth and 144gmacs dsp processing power in chip-scale packaging make the kintex-7 70t fpga highly effective for both front- and back-end ultrasound processing. designers can deploy a fully programmable 128-channel ultrasound implementation that scales up to 196 or 256 channels for high-end cart solutions or down to 64 or 32 channels for hand-held solutions.

• 128-channel implementation in a modular set of five kintex-7 70t fpgas offers 44% lower power, 45% lower cost, and 57% smaller form factor compared to previous-generation fpgas

• kintex-7 70t fpgas offer 144gmacs from 240 dsp slices (288gmacs for symmetric filters)

• built-in support for eight pci express gen1/gen2 channels enables high-bandwidth interface to host system

• chip-scale packaging for small form factor

圖2.手持超聲波框圖

kintex-7 fpgas enable cost-effective, low-power bridging of the serial digital interface (sdi) protocol onto ip technology for long-distance wan transport to link local studios/live events, broadcast facilities, and satellite uplink stations using standard ip networks.

• reduce power by 64% and reduce cost by 85% with a single xc7k160t fpga implementation of a 12x 3g-sdi over 4x10gbe bridge compared to the equivalent function implemented in two virtex-6 xc6l130t devices

• reduce cost further with high-bandwidth interfaces that shrink bom: 72-bit x 1,600mbps ddr3 memory interface capability enables a single memory buffer that would require two or four memory buffers in previous-generation fpgas.

圖3.ip網(wǎng)關視頻框圖

kintex-7 mini module plus開發(fā)套件

the kintex-7 mini module plus development kit provides a complete hardware environment for designers to accelerate their time to market. the kit delivers a stable platform to develop and test designs targeted to the high-performance and low-power xilinx kintex-7 325t fpga. the installed kintex-7 325t device offers a prototyping environment to effectively demonstrate the enhanced benefits of mid-range cost xilinx fpga solutions. reference designs are included with the kit to exercise standard peripherals on the evaluation board for a quick start to device familiarization.

kintex-7 mini module plus開發(fā)套件主要特性:

xilinx fpga devices supported

— xilinx kintex-7 xc7k160t-1ffg676 fpga

— xilinx kintex-7 xc7k325t-1ffg676 fpga (only option currently available)

— xilinx kintex-7 xc7k410t-1ffg676 fpga

i/o connectors

— one mini module plus interface with jx1 / jx2 signal / power connectors, and jx3 power sense.

— one 20 pin xadc analog header

— one 10/100/1000 rj-45 ethernet connector

— one usb3 micro b connector

— one usb3 jtag fly-wire header

gtx transceivers accessed through jx1/jx2

— one pci express interface 4 lanes @ 5.0 gbps (pci express 2.0)

— four single lane general-purpose mgt.  memory

— 256mb of ddr3 memory (64m x 32) at 1600 mbps

— 64 mb of flash memory in master bpi configuration with a 50 mhz user cclk.

— 8kb of i2c eeprom

— 128kb of i2c eeprom dedicated to ez-usb fx3 superspeed usb controller

communication

— ez-usb fx3 superspeed usb controller

— 10/100/1000 phy interface

— rs232 port accessed through jx1/jx2

— jtag port accessed through jx1/jx2  clocks

— 200mhz lvds clock source

— programmable lvds clock source (mgt reference clock input)

— emc lvcmos 50mhz clock source

— dedicated 50mhz and 25mhz clock sources

— two mgt reference clock inputs available through jx1/jx2

— four differential clock inputs available through jx1/jx2

— dedicated phy receive and 125mhz clocks  user i/o

— 118 differential io available through jx1/jx2  power

— regulated 3.3, 2.5, 1.8, 1.5, 1.2, 1.0 v supply voltages must be supplied through jx1/jx2

— regulated 5.0, 1.8, 1.25 v analog supply voltages are generated on board configuration

— jtag port accessed through jx1/jx2

圖4.裝配好kintex-7 mini module plus開發(fā)套件外形圖(不含電源或電纜)

圖5.kintex-7 mini module plus框圖

圖6.kintex-7 mini module plus板電源框圖

圖7.kintex-7 mini module plus板電路圖(1)

圖8.kintex-7 mini module plus板電路圖(2)

圖9.kintex-7 mini module plus板電路圖(3)

圖10.kintex-7 mini module plus板電路圖(4)

圖11.kintex-7 mini module plus板電路圖(5)

圖12.kintex-7 mini module plus板電路圖(6)

圖13.kintex-7 mini module plus板電路圖(7)

圖14.kintex-7 mini module plus板電路圖(8)

圖15.kintex-7 mini module plus板電路圖(9)

圖16.kintex-7 mini module plus板電路圖(10)
kintex-7 mini module plus板材料清單:


xilinx公司的kintex-7 fpga具有144gmacs dsp,能滿足更高的性能而功耗是目前產(chǎn)品的40%,可以集成更多的硅器件,從而更容易創(chuàng)建差異性產(chǎn)品,具有更低的成本而提高了競爭性.可編程的kintex-7 fpga支持多種空中接口如lte,wimax和wcdma.廣泛用在通信,醫(yī)療電子,3d tv,航空航天,多模式無線電等.本文介紹了kintex-7 fpga主要特性以及單片lte基帶(2x4mimo)框圖,手持超聲波框圖和ip網(wǎng)關視頻框圖與kintex-7 mini module plus開發(fā)套件主要特性,框圖和板電源框圖,開發(fā)套件電路圖和材料清單.